set_property SLEW SLOW [get_ports led]

set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property PACKAGE_PIN N17 [get_ports led]

set_property IOSTANDARD LVCMOS33 [get_ports rstn_in]
set_property PACKAGE_PIN M4 [get_ports rstn_in]


#If the following clock constraints are used for the SRAM FPGA board
#set_property PACKAGE_PIN U22 [get_ports clk_in]

#If the following clock constraints are used for the DDR FPGA board
set_property PACKAGE_PIN D18 [get_ports clk_in]

set_property IOSTANDARD LVCMOS33 [get_ports clk_in]

set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]




